[UVM源代码研究] 聊聊寄存器模型的uvm_reg_adapter

//------------------------------------------------------------------------------//// Class: uvm_reg_adapter//// This class defines an interface for converting between <uvm_reg_bus_op>// and a specific bus transaction. //------------------------------------------------------------------------------virtual class uvm_reg_adapter extends uvm_object;  // Function: new  //  // Create a new instance of this type, giving it the optional ~name~.  function new(string name="");    super.new(name);  endfunction  // Variable: supports_byte_enable  //  // Set this bit in extensions of this class if the bus protocol supports  // byte enables.  bit supports_byte_enable;  // Variable: provides_responses  //  // Set this bit in extensions of this class if the bus driver provides  // separate response items.  bit provides_responses;   // Variable: parent_sequence  //  // Set this member in extensions of this class if the bus driver requires  // bus items be executed via a particular sequence base type. The sequence  // assigned to this member must implement do_clone().  uvm_sequence_base parent_sequence;   // Function: reg2bus  //  // Extensions of this class ~must~ implement this method to convert the specified  // <uvm_reg_bus_op> to a corresponding <uvm_sequence_item> subtype that defines the bus  // transaction.  //  // The method must allocate a new bus-specific <uvm_sequence_item>,  // assign its members from  // the corresponding members from the given generic ~rw~ bus operation, then  // return it.  pure virtual function uvm_sequence_item reg2bus(constref uvm_reg_bus_op rw);  // Function: bus2reg  //  // Extensions of this class ~must~ implement this method to copy members  // of the given bus-specific ~bus_item~ to corresponding members of the provided  // ~bus_rw~ instance. Unlike <reg2bus>, the resulting transaction  // is not allocated from scratch. This is to accommodate applications  // where the bus response must be returned in the original request.  pure virtual function voidbus2reg(uvm_sequence_item bus_item,                                     ref uvm_reg_bus_op rw);  local uvm_reg_item m_item;  // function: get_item  //  // Returns the bus-independent read/write information that corresponds to  // the generic bus transaction currently translated to a bus-specific  // transaction.  // This function returns a value reference only when called in the  // <uvm_reg_adapter::reg2bus()> method.  // It returns null at all other times.  // The content of the return <uvm_reg_item> instance must not be modified  // and used strictly to obtain additional information about the operation.    virtual function uvm_reg_item get_item();    return m_item;  endfunction  virtual function void m_set_item(uvm_reg_item item);    m_item = item;  endfunctionendclass

//------------------------------------------------------------------------------//// CLASS: uvm_reg_bus_op//// Struct that defines a generic bus transaction for register and memory accesses, having// ~kind~ (read or write), ~address~, ~data~, and ~byte enable~ information.// If the bus is narrower than the register or memory location being accessed,// there will be multiple of these bus operations for every abstract// <uvm_reg_item> transaction. In this case, ~data~ represents the portion // of <uvm_reg_item::value> being transferred during this bus cycle. // If the bus is wide enough to perform the register or memory operation in// a single cycle, ~data~ will be the same as <uvm_reg_item::value>.//------------------------------------------------------------------------------typedef struct {  // Variable: kind  //  // Kind of access: READ or WRITE.  //  uvm_access_e kind;  // Variable: addr  //  // The bus address.  //  uvm_reg_addr_t addr;  // Variable: data  //  // The data to write. If the bus width is smaller than the register or  // memory width, ~data~ represents only the portion of ~value~ that is  // being transferred this bus cycle.  //  uvm_reg_data_t data;  // Variable: n_bits  //  // The number of bits of <uvm_reg_item::value> being transferred by  // this transaction.  int n_bits;  /*  constraint valid_n_bits {     n_bits > 0;     n_bits <= `UVM_REG_DATA_WIDTH;  }  */  // Variable: byte_en  //  // Enables for the byte lanes on the bus. Meaningful only when the  // bus supports byte enables and the operation originates from a field  // write/read.  //  uvm_reg_byte_en_t byte_en;  // Variable: status  //  // The result of the transaction: UVM_IS_OK, UVM_HAS_X, UVM_NOT_OK.  // See <uvm_status_e>.  //  uvm_status_e status;} uvm_reg_bus_op;

// Enum: uvm_access_e//// Type of operation begin performed//// UVM_READ     - Read operation// UVM_WRITE    - Write operation//   typedef enum {      UVM_READ,      UVM_WRITE,      UVM_BURST_READ,      UVM_BURST_WRITE   } uvm_access_e;

// Type: uvm_reg_addr_logic_t//// 4-state address value with <`UVM_REG_ADDR_WIDTH> bits//typedef  logic unsigned [`UVM_REG_ADDR_WIDTH-1:0]  uvm_reg_addr_logic_t ;

// Type: uvm_reg_data_t//// 2-state data value with <`UVM_REG_DATA_WIDTH> bits//typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t ;

// Type: uvm_reg_byte_en_t//// 2-state byte_enable value with <`UVM_REG_BYTENABLE_WIDTH> bits//typedef  bit unsigned [`UVM_REG_BYTENABLE_WIDTH-1:0]  uvm_reg_byte_en_t ;

// Enum: uvm_status_e//// Return status for register operations//// UVM_IS_OK      - Operation completed successfully// UVM_NOT_OK     - Operation completed with error// UVM_HAS_X      - Operation completed successfully bit had unknown bits.//   typedef enum {      UVM_IS_OK,      UVM_NOT_OK,      UVM_HAS_X   } uvm_status_e;

`ifndef SPI_ADAPTER__SV`define SPI_ADAPTER__SVclass spi_adapter extends uvm_reg_adapter;   `uvm_object_utils(spi_adapter)   function new (string name="");      super.new(name);   endfunction   virtual function uvm_sequence_item(const ref uvm_reg_bus_op rw);      spi_transfer tr;	  tr = spi_transfer::type_id::create("tr");	  tr.randomize() with {	     wdata.size() == 2;		 if(rw.kink == UVM_WRITE) {		    wdata[0][7] == 1;			wdata[1] = rw.data		 }		 else {		    wdata[0][7] == 0;		 }		 wdata[0][6:0] = rw.addr;	  };	  return tr;   endfunction   virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op);      spi_transfer tr;	  if(!$cast(tr, bus_item)) begin	     `uvm_fatal("TYPE_FATAL", "bus_item doesn't match!")	  end	  if(tr.wdata[0][7] == 0) begin	     rw.kind = UVM_READ;	  end	  else begin	     rw.kind = UVM_WRITE;	  end	  rw.addr = tr.wdata[0][6:0];	  rw.data = tr.rdata[1];	  rw.status = UVM_IS_OK;   endfunctionendclass`endif

`ifndef APB_ADAPTER__SV`define APB_ADAPTER__SVclass apb_adapter extends uvm_reg_adapter;   `uvm_object_utils(apb_adapter)   function new (string name="");      super.new(name);   endfunction   virtual function uvm_sequence_item(const ref uvm_reg_bus_op rw);      apb_transfer tr;	  tr = apb_transfer::type_id::create("tr");	  tr.dir   = (rw.kind == UVM_WRITE) ? APB_WRITE : APB_READ;	  tr.addr  = rw.addr;	  tr.wdata = rw.data;	  return tr;   endfunction   virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op);      apb_transfer tr;	  if(!$cast(tr, bus_item)) begin	     `uvm_fatal("TYPE_FATAL", "bus_item doesn't match!")	  end	  	  rw.kind = (tr.dir == APB_READ) ? UVM_READ : UVM_WRITE ;	  rw.addr = tr.addr;	  rw.data = tr.rdata;	  rw.status = UVM_IS_OK;   endfunctionendclass`endif

`ifndef TILELINKE_ADAPTER__SV`define TILELINKE_ADAPTER__SV`ifndef SOURCE   `define SOURCE 6`endifclasstilelink_adapterextendsuvm_reg_adapter;   bit [`SOURCE-1 : 0] valid_source;   `uvm_object_utils(tilelink_adapter)   function new (string name="");      super.new(name);      support_byte_enable = 1;      provides_responses  = 1;   endfunction   virtual function uvm_sequence_item(const ref uvm_reg_bus_op rw);      tilelink_sequence_item tr;      tr = tilelink_sequence_item::type_id::create("tr");      tr.randomize() with (a_size == 2; burst_num == 1;);      tr.a_opcode = (rw.kind == UVM_WRITE) ? PutFullData : Get;      tr.a_address  = rw.addr;      if(`UVM_REG_DATA_WIDTH == 32) begin         tr.a_data[0] = rw.data;         tr.a_mask[0] = rw.byte_en;      end      else if(`UVM_REG_DATA_WIDTH == 64) begin         tr.a_data[0] = {rw.data, rw.data};         if(rw.addr % 8 == 0) begin            tr.a_mask[0] = {4'b0, rw.byte_en};         end         else begin            tr.a_mask[0] = {rw.byte_en, 4'b0};         end      end      tr.a_source = valid_source;      return tr;   endfunction   virtual functionvoidbus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op);      tilelink_sequence_item tr;      if(!$cast(tr, bus_item)) begin         `uvm_fatal("TYPE_FATAL", "bus_item doesn't match!")      end      rw.kind = (tr.a_opcode == Get) ? UVM_READ : UVM_WRITE ;      rw.addr = tr.a_address;      if(`UVM_REG_DATA_WIDTH == 32) begin         rw.data    = tr.d_data[0];         rw.byte_en = tr.a_mask[0];      end      else if(`UVM_REG_DATA_WIDTH == 64) begin         if(tr.a_address % 8 == 0) begin            rw.byte_en = tr.a_mask[0][3:0];            rw.data    = tr.d_data[0][31:0];         end         else begin            rw.byte_en = tr.a_mask[0][7:4];            rw.data    = tr.d_data[0][63:32];         end      end      foreach(tr.d_corrupt[i]) begin         if(tr.d_corrupt[i] == 1) begin            rw.status = UVM_NOT_OK;            `uvm_warning("bus2reg", "bus corrupt!")            break;          end          else begin             rw.status = UVM_IS_OK;             continue;          end      end   endfunctionendclass`endif